1. Field of the Invention
Embodiments of the invention generally relate to electronics, and in particular, to network clocking.
2. Description of the Related Art
Digital telecommunication and data communication networks are formed from a number of nodes, each of which may have different functions. In most networks, signals are interchanged between nodes using serial bit streams. Typically, a clock signal is recovered from a received serial bit stream, and the clock signal is then used to synchronize and extract data from the incoming data stream.
FIG. 1 illustrates a conventional example of a serializer/deserializer or SerDes, which is a combination of a serializer and a deserializer. A serializer is a circuit block that converts a parallel word stream into a serial bit stream. A deserializer is circuit block that converts a serial bit stream into a parallel word stream with a recovered clock signal.
The transmit (serializer) portion includes a clock synthesizer 102, a parallel/serial converter 104, and a transmitter (TX) 106. The clock synthesizer 102 generates a transmit clock by multiplying the frequency of a reference clock signal 108. Parallel transmit data words 110 are synchronized by a divided-down version of the transmit clock and are converted to a serial bit stream by the parallel/serial converter 104 that is then typically provided off chip as an output by the transmitter (TX) 106.
The receive (deserializer) portion includes a receiver (RX) 122, a clock recovery circuit 124, and a serial/parallel converter 126. The serial bit stream is brought on-chip and conditioned by the receiver (RX) 122, and a clock signal is recovered by the clock recovery circuit 124. The data is then converted to a series of parallel words 128 by a serial/parallel converter 126, which are synchronized by a divided-down version of the recovered clock signal.
In many modern practical SerDes, the clock synthesizer 102 also drives the clock recovery circuit 124, in effect training the clock recovery circuit 124 to operate at an appropriate frequency. This concept is represented the dotted line 132 from the clock synthesizer 102 to the clock recovery circuit 124.
FIG. 2 illustrates a conventional example of a phase-locked loop (PLL). A PLL is a fundamental block that is often used to process the clock signals in a SerDes. A PLL has three major elements: a phase detector 202, a loop filter 204, and a controlled oscillator 206. Depending upon the application of the PLL, the phase detector 202, loop filter 204, and controlled oscillator 206 can be implemented in a number of different ways, ranging from fully-analog implementations to fully-digital asynchronous implementations, to fully-digital synchronous implementations, with many intermediate implementations that incorporate aspects of one or more of the other implementations, with varying levels of implementation and integration complexity. In conventional SerDes implementations, there are typically at least two PLLs. A first PLL performs the clock synthesis function, while a second performs the clock recovery function.
FIG. 3 illustrates a conventional example for the clock synthesizer 102 implemented with a clock synthesis PLL. The clock synthesizer 102 multiplies the reference clock signal 108, which typically operates in the tens to hundreds of megahertz, up to a line-rate transmit clock signal, typically in the gigahertz, which is used to clock serial data out from the SerDes. An integer frequency divider 302 in the feedback path, a phase/frequency detector 304 and a loop filter 306 operate such that the output frequency Fout of a controlled oscillator 308 is an integer-multiplied version of the incoming reference Fref. The phase/frequency detector 304 is a type of phase detector.
FIG. 4 illustrates another conventional example for the clock synthesizer 102. By incorporating additional dividers 402, 404 on the PLL input and/or on the PLL output as shown in FIG. 4, a number of different possible output clock frequencies can be synthesized, such as frequencies that are simple integer ratios of the various dividers. In clock synthesis PLLs, the loop filter 306 and the controlled oscillator 308 are typically analog circuits, with the loop filter 306 being a resistor-capacitor network and the controlled oscillator 308 usually being an analog voltage-controlled oscillator (VCO); however there are many alternatives known to those of ordinary skill in the art. In addition, other techniques exist, such as the use of controlled delay lines and Delay-Locked Loops (DLLs) that can be used to construct the clock synthesizer 102.
FIG. 5 illustrates a conventional example of a clock recovery circuit based on a clock recovery PLL. In the context of a SerDes, the clock recovery circuit recovers the clock signal from the serial bit stream that is being provided as an input to the SerDes. The clock recovery PLL uses a phase detector 502 and a loop filter 504 to control a controlled oscillator 506 to recover a recovered clock signal 508 that is synchronized to the incoming data bit stream 510. The recovered clock signal 508 is then used to re-sample and re-synchronize the incoming data bit stream 510 using a D-type flip-flip DFF 512. In older-generation SerDes circuits, the loop filter 504 and the controlled oscillator 506 were typically implemented using a resistor-capacitor network and a VCO, respectively.
FIG. 6 illustrates another conventional example of a clock recovery circuit. In a modern SerDes, the loop filter 504 for the clock recovery circuit is typically implemented using a digital signal processing (DSP) filter. The controlled oscillator 506 illustrated in FIG. 5 is implemented with a clock synthesizer 602 and a phase rotator 604. The clock synthesizer 602 generates a fixed frequency clock signal, which is adjusted or phase rotated by the phase rotator 604 to generate the recovered clock signal 508. The phase rotator 604 can be implemented by a variety of techniques, such as, fully synchronous dividers, multiple-phase generation and picking, phase interpolation, single-side-band (SSB) modulators, and the like. The circuit of FIG. 6 is generally recognized to be both smaller in area and lower in power consumption than older analog circuit implementations.
Most PLLs, including those used for clock synthesis and clock recovery, are described as having low-pass transfer functions. Clock synthesizers and clock recovery circuits that are constructed without PLLs can also be described with low-pass transfer functions, and are typically analyzed in a similar manner to those with PLLs.
A transfer function describes the response of a PLL to a small-signal modulation of the input frequency to the output frequency. In networking theory, the transfer function is often referred to as a jitter transfer function (JTF). A PLL's bandwidth normally refers to the corner frequency of the low-pass JTF, which describes the frequency band in which jitter or noise on the incoming clock signal or in the feedback dividers will be transferred to the output. At the same time, the PLL bandwidth (corner frequency) normally can be used to construct a second transfer function, which describes the gain from components within the loop (phase detector 502, the loop filter 504, the controlled oscillator 506, 602/604, etc) to the output. Typically, the second transfer function characteristic is that of a high-pass filter having the same bandwidth (corner frequency) as the low-pass filter, where noise below the bandwidth (corner frequency) should be filtered out by the PLL itself. As a result of these two transfer functions, there is a tradeoff between the two differently-filtered types of jitter, meaning that there is an optimum PLL bandwidth to minimize the total jitter at the output from the PLL. For non-PLL-based clock synthesis and clock recovery, the second transfer function may take a slightly different form, which changes optimization criteria slightly, but not obviate the need for optimization.
In most applications, a clock synthesizer will have a relatively high bandwidth, typically measured in hundreds of kilohertz (kHz) to low single-digit megahertz (MHz), depending upon many factors. A clock recovery circuit will typically have an extremely wide bandwidth, often 1 or 2 orders of magnitude higher than the bandwidth of the accompanying clock synthesizer. A wide bandwidth is used for robust SerDes operation in the presence of channel impairments.
It can be difficult to implement an extremely low bandwidth fully-analog PLLs in an integrated circuit. The narrow bandwidth typically requires relatively large loop filter components, and the intrinsic jitter of available on-chip oscillators (generally multi-vibrators, ring oscillators or LC-tank oscillators) can be prohibitively large. As a result, low bandwidth PLLs are usually either constructed using discrete components on a board or are not constructed using analog techniques.
Non-idealities can accompany a wide bandwidth selection for clock recovery. These non-idealities can include jitter peaking (noise gain at certain frequencies) and non-linear and quantization effects that come from a modern DSP-based SerDes clock recovery, particularly from non-PLL-based solutions. If the recovered clock signal from one link were to be used directly as the transmit clock signal for another link, the receiver at the end of that second link would experience the jitter from the first link's clock recovery, and will add its own non-idealities to the clock signal, which is a process known as jitter accumulation. After a certain number of such links with jitter accumulation, there is likely to be an excessive amount of jitter at certain frequencies that will cause the link to fail. As a result, it is generally not a good design practice to use a recovered clock to directly clock a transmitter.
Most clock synthesis PLLs, including those shown in FIG. 4, are what is termed Integer-N PLLs. In PLLs like this, the frequency resolution of the output is determined by a ratio of integer divide ratios. By programming the dividers separately at different times it is possible to produce different output frequencies. The use of relatively large dividers, in particular at the pre-divider 402 (FIG. 4), permits relatively fine frequency resolution at the output to be achieved. However the foregoing technique limits the bandwidth of the PLL. In general, practical clock synthesis PLLs have a maximum bandwidth that is approximately one tenth of the reference clock frequency. When the pre-divider 402 is used, the reference clock frequency to the PLL is effectively divided by the pre-divider amount, which limits the maximum bandwidth of the PLL to as low as 100 Hz or lower for the finest-resolution PLLs.
FIG. 7 illustrates a fractional-N PLL, which is an alternative to a low-bandwidth Integer-N clock synthesis PLL. A dashed box outlines components for a fractional-N synthesizer 700. In a fractional-N PLL, a feedback divider 702 is controlled and is modulated by a fractional-N modulator 704 such that the feedback divider 702 can divide by X, where X is an integer that may change between successive divide cycles. The fractional-N modulator 704 can be a digital state machine that generates a long-term average feedback mean(X)= X divider ratio selected by an additional control, typically a rational fraction of two typically large integers: numerator n; and denominator d, such that
      X    _    =            n      d        .  The illustrated fractional-N modulator uses an output of the feedback divider 702 for clocking of the state machine; however, other configurations are possible.
The modulation of the feedback divider 702 from the fractional-N modulator 704 introduces additional jitter at the input of the phase/frequency detector 304, so the additional jitter should be low-pass filtered by the PLL loop just as if it had been jitter on the input clock signal Fref. If the additional jitter is mostly of a high-frequency jitter characteristic, the PLL's low-pass filter operation should remove the majority of the jitter from the output without requiring an extremely low PLL bandwidth. The required bandwidth of a fractional-N clock synthesis PLL is typically at least an order of magnitude smaller than that of an integer-N PLL; however in many PLL configurations, the bandwidth used for optimum PLL output jitter is often similar for the two types so the distinction makes very little practical difference. In order to ensure that the feedback divider jitter is at high frequency, most practical fractional-N PLLs use a Delta-Sigma modulator (or something similar) to modulate the feedback divider 702. While fractional-N techniques can be used without a PLL, most practical fractional-N clock synthesizers are implemented with PLLs because the low-pass transfer function of a PLL provides significant benefits for output jitter.
FIG. 8 illustrates a loop-timed SerDes with a jitter attenuator (JAT) 802. Circuits for startup are not shown in FIG. 8, but are well known to those of ordinary skill in the art. Loop-timing is used in some applications, such as in synchronous and asynchronous networks. With loop-timing, the recovered clock signal from an incoming serial data stream is used as the transmit clock signal for one or more outgoing serial streams. The JAT 802 prevents jitter accumulation by filtering the recovered clock signal. The JAT 802 is disposed in the signal path between the clock recovery circuit 124 and the clock synthesizer 102 (with possible other intervening components, such as a divider).
If the clock synthesizer's bandwidth were low enough, the JAT 802 would not be used, however in most practical systems the bandwidth used to filter the recovered clock signal from the clock recovery circuit 124 is one or two orders of magnitude (and often more) lower than the optimum minimum-jitter bandwidth of the clock synthesizer 102. The JAT 802 should have a relatively low bandwidth to filter the recovered clock signal, have exhibit relatively little jitter peaking, and should minimize jitter accumulation. The JAT 802 is typically implemented using a PLL.
In synchronous networking, a clock signal is typically distributed from a single master clock source located at one node. The clock reference can be distributed from that node to the entire network using a hierarchy of clock distribution. The clock signals are typically distributed via data links with clock signals recovered at the receive end. As a result, a node synchronizes its local transmit clock signal to an incoming clock signal from a node closer to the master clock source, and the entire system is effectively loop timed such that each node uses the clock recovery circuit 124 and the JAT 802 for clock distribution.
FIG. 9 illustrates two SerDes 900, 902 operating in a transport timing mode over a network 904. Transport timing refers to the transport of network synchronization, clocks, or data across a network 904 whose underlying clock reference may be asynchronous and unrelated to the clock reference of the information being transported. At an ingress node SerDes 900, recovered data is encoded for transport over the network 904, while the recovered clock signal is measured by a measurement block 906 and is also encoded for transport with the data over the network 904. At the egress node, the clock measurements are used to reproduce the recovered clock signal in the clock regeneration block 908, which is then used as the reference for the egress node SerDes 902. FIG. 9 illustrates a bi-directional link, where information is transported back through the network system through SerDes 902, clock measurement block 910, network 904, clock regeneration block 912, and SerDes 900; however unidirectional links may also be transport timed. For clarity, circuitry for startup is not shown, but is well known to those of ordinary skill in the art.
Various techniques can be used to measure the asynchronous clock signal at the ingress node to a network, and to transport the measurement across the network. Regenerating the clock signal at an egress node typically requires a block with some similarity to the loop-timed JAT 802 (FIG. 8). Because network timing updates can be irregularly spaced over time, transport timing should be used with a filter having a relatively low bandwidth, such as less than 100 Hz or even less than 10 Hz, to reduce jitter coming from the network. Because transport timing is open loop, additional techniques, such as loop timing, are used to keep the local reference clock signals of the ingress and egress nodes synchronized or to ensure that the frequency differences are known and bounded.
Clock holdover is another feature of synchronous network clocking Clock holdover refers to a feature in which a node remains frequency locked for a period of time even if its incoming reference clock signal is removed or unavailable. In most practical networks, there are hierarchies of frequency references with redundant distribution paths, such that if one master clock source or path becomes unavailable, the nodes will switch over to another master clock. Depending upon the application and its requirements, clock holdover can place frequency accuracy requirements between ±10 parts per billion to ±10 parts per million over timescales measured between minutes and days without a master reference.
Clock holdover is typically implemented as a requirement of the JAT 802, such that in the absence of a recovered master clock source, the JAT 802 should hold its output frequency relatively steady until an alternate master clock source can be used.
As discussed earlier, the JAT 802 is typically implemented using a low-bandwidth PLL. Low-bandwidth PLLs, and in particular, low-bandwidth analog PLLs, can be difficult to implement. In general, low-bandwidth PLLs reject relatively little noise from the oscillator, and use relatively large loop filter components. As a result, integrated low-bandwidth PLLs tend to be large and exhibit relatively large output jitter. Thus, integrated circuits techniques were not initially used for implementation of the JAT 802. Rather, external loop filter components and controlled oscillators, such as voltage-controlled surface acoustic wave oscillators (VCSO) or voltage-controlled crystal oscillators (VCXO) had been used. Those solutions can be cost prohibitive and can make it impractical to implement in a high-density device.
FIG. 10 illustrates a conventional example of an integrated loop-timed JAT that uses a digital PLL rather than an analog PLL. A digital PLL is formed by a digital phase detector 1002, a digital JAT loop filter 1004, a numerically-controlled oscillator (NCO) 1006, the clock synthesizer 102 and the clock recovery circuit 124. The clock synthesizer 102 and the clock recovery circuit 124 can correspond to the same blocks described earlier in connection with FIGS. 1 and 8, while the NCO 1006 can be as simple as a programmable digital divider running from a low-frequency reference clock or may be significantly more complex. The NCO 1006 can include techniques such as the use of a high-frequency multi-GHz reference clock, multiple phases of a reference clock, programmable delay lines, or other techniques similar to those described earlier in connection with the phase rotator 604 (FIG. 6).
A JAT 1000 is formed by the digital phase detector 1002, the digital JAT loop filter 1004, the NCO 1006. The digital phase detector 1002 and the digital loop filter 1004 drive the NCO 1006. An output of the NCO 1006 is used as the reference signal for the clock synthesizer 102. The output of the clock synthesizer 102, via the clock recovery circuit 124, is provided as an input to the digital phase detector 1002 to close a feedback loop and to phase and frequency lock the outputs of the clock recovery circuit 124 and the clock synthesizer 102 together.
By using a digital (DSP-based) loop filter, the low-bandwidth requirement of the JAT can be readily achieved. However, simple forms of the NCO 1006, such as those where the NCO 1006 is an digital divider is driven from a low frequency reference clock, can generate a relatively large amount of output jitter, which requires the clock synthesizer 102 to have a low bandwidth to attenuate this jitter, which complicates the specification and design of the clock synthesizer 102.
As an alternative to reducing the bandwidth of the clock synthesizer 102, the NCO's output jitter can be reduced by using a second optional clock synthesizer 1008, which allows the NCO 1006 to provide finer-resolution (and lower jitter) clocks at its output. This second clock synthesizer 1008 typically multiplies a reference clock signal's frequency to a higher frequency in order to provide a stable high-frequency clock to the NCO 1006. The bandwidth of the clock synthesizer 102 can then be increased, which simplifies its design and allows it to be better optimized in isolation from the JAT. The NCO's output jitter can be further reduced by using multiple phases from the second clock synthesizer 1008 or by using more complex NCO configurations, such as programmable delay lines or techniques similar to those described earlier in connection with the phase rotator 604 (FIG. 6).
Jitter accumulation is an issue with the circuit illustrated in FIG. 10. The cascading of the clock recovery circuit 124, the NCO 1006, and the two clock synthesizers 102, 1008, results in jitter accumulating through the system, which both increases jitter on the output and makes it more difficult to specify and measure jitter. In addition, the use of the second clock synthesizer 1008 and/or a complex NCO 1006 adds area and power to the overall circuit.
FIG. 11 illustrates a transport timing circuit for a jitter attenuator (JAT) 1100 with a similar topology to the circuit of FIG. 10. Instead of the digital phase detector 1002 (FIG. 10) used in the loop-timed JAT, a clock measurement packet decoder block 1102 interprets incoming timing measurements and drives a digital filter 1104, which drives the NCO 1006 as in FIG. 10. The discussion of jitter in connection with FIG. 10 is also applicable to the circuit illustrated in FIG. 11.
Clock holdover requirements for either loop-timed or transport-timed applications are similar. In the absence of a recovered clock signal or network timing packets, the digital JAT loop filter 1004 can hold its previous value and drive the NCO 1006 at a fixed frequency, provided there is a stable reference clock frequency. As a result, if the intrinsic jitter at the output of the clock synthesizer 102 meets the requirements and if the reference clock frequency is stable, the circuits of FIG. 10 and FIG. 11 can meet clock holdover requirements. If the reference clock frequency is not stable, but is instead variable with a measurable external input, such as temperature, clock holdover performance can be improved by measuring the external input and compensating for the variation.